The GRACE Project Intro
Astrophysical Computer Simulations using Programmable Hardware
Recent News:
-
December 2009:
Workshop
Accelerator-based Computing and Manycore
(Manycore and Accelerator-based Computing for Physics and Astronomy Applications),
jointly organised by
Hemant Shukla and
John Shalf
(LBL/NERSC) ,
Tom Abel (KIPAC/Stanford)
with Rainer Spurzem (GRACE Teams), at
Kavli Institute for
Particle Astrophysics and Cosmology (KIPAC) . In this workshop future
transcontinental cooperation on software and hardware issues for novel many-core
systems will be prepared, in which the GRACE-2 proposed project will play an
important role.
-
September 2009: :
Rainer Spurzem appointed special visiting professor of Chinese Academy of Sciences, at
National Astronomical Observatories of China , to
build a computational astrophysics group and supervise the design and operation of a
special accelerated supercomputer with 170 Tesla GPU's at NAOC (joint appointment with
Kavli Institute of Astronomy and Astrophysics
of at Peking University, China . The project is
called the Silk Road Project . In this project
also FPGA based accelerator cards MPRACE will be used and further explored as a follow-up
of the GRACE project and in collaboration with the other GRACE teams.
-
June 2009:
GRACE project presented at invited talk of Rainer Spurzem during the
International Supercomputing
Conference in Hamburg in June 2009, titled
Accelerating Astrophysical Particle Simulations with Programmable Hardware (FPGA & GPU) .
-
March 2009: Peter Berczik obtained record benchmark of sustained 25 Teraflop/s for a
single five million body direct N-body simulation
on 100 Tesla graphical processing units (GPU) on the GPU clusters of the
Institute of Process Engineering IPE
of Chinese Academy of Sciences in Beijing in March 2009.
The IPE is operating of order
1000 GPU cards with a cumulated peak speed of 1 Petaflop/s. It's hardware is the prototype
for similar clusters to be opened at other CAS institutions (see top news).
See preliminary plot
(this work is
in collaboration with
Keigo Nitadori and
Tsuyoshi Hamada , and also partly shows results
obtained from the kolob frontier
kolob frontier GPU cluster see below.
-
November 2008:
Kolob - First Supercomputer based on Graphical Processing Units at Heidelberg University
(see
University of Heidelberg Press Notice );
The project is funded by the
University of Heidelberg Excellence Scheme ,
in collaboration with
Ralf Klessen ,
Robi Banerjee
(ITA) and
Reiner Männer ,
Andreas Kugel ,
Guillermo Marcus
(ZITI) .
Graphic cards (=GPU: graphical processing units) offer a huge power for parallel computing tasks, which accelerates traditional processors, as they are used in standard PCs.
-
April 2008: Gravitational Waves visualized
from Black Hole Merger in GRACE Cluster titan (April 2008, avi-File 95 MB)
... more news ...
GRACE is an interdisciplinary project of theoretical astrophysics and computer engineering to
use reconfigurable hardware (FPGA = field programmable gate array) for astrophysical particle
simulations.
Teams of
Astronomisches Rechen-Institut, Zentrum für Astronomie Univ. Heidelberg (ARI-ZAH) ,
Lehrstuhl V, Central Institute for Computer Engineering (ZITI), Univ. Heidelberg, Location Mannheim (ZITI)
and
Lehrstuhl Computational Astrophysics (CAST)
at the
Universitätssternwarte München (USM)
collaborate to use
Programmable Hardware (FPGA) for gravitational and non-gravitational force computations
(e.g. for smoothed particle hydrodynamics SPH) in particle based large scale
astrophysical computer simulations.
The dynamics of galactic nuclei with black
holes, of merging galaxies, of star formation is modelled using this new computer architecture. Our main
international collaborators are David Merritt and
Hans-Peter Bischof with the
GRAPEcluster at RIT as well as
Naohito Nakasato, nakasato@riken.jp and
Tsuyoshi Hamada, thamada@riken.jp , and the
PROGRAPE/PGR project , RIKEN Japan
The GRACE cluster ''titan''
at the
ARI
ZAH (Heidelberg, Germany)
was assembled and delivered by
sysgen GmbH

using MPRACE Boards
of UMA
with Xilinx Virtex-2
FPGA hardware
(see the Mannheim FPGA Webpage );
micro-GRAPE6
hardware, produced by
Hamamatsu Metrix Co. Japan
Last updated: July 2008. Please send comments to: spurzem@ari.uni-heidelberg.de.